Recently, nonvolatile memories that are data rewritable semiconductor devices have been widely used for the storage of electronic data. FIG. 1 shows the sense amp configuration of a nonvolatile semiconductor memory device disclosed in Japanese Unexamined Patent Publication No. 2002-237193. This configuration includes a detecting unit 130 disposed on the side of a memory cell (data cell), a detecting unit 132 disposed on the side of a reference cell, and a differential amplifier unit 134. If a wordline WLARY is selected and a Y gate YG101 is turned ON by a gate signal YGARY, the detecting unit 130 detects the current of a memory cell MC101 and converts the detected current into voltage. The detected data (voltage) is output from a node SENSEARY. If a wordline WLREF is selected and a Y gate YG102 is turned ON by a gate signal YGREF, the detecting unit 132 detects the current of a reference cell MC102 and converts the detected current into voltage. The detected data (voltage) is output from a node SENSEREF. Then, the output voltage of the detecting unit 130 is compared with the output voltage of the detecting unit 132 coupled to the reference cell, using the differential amplifier unit 134 to determine whether the data is “1” or “0.”
However, the conventional art illustrated in FIG. 1 does not teach the correlation between the device characteristics (structures, sizes, etc.) of transistor elements in which the same current flows. For instance, neither the relationship between the characteristics of the NMOS diode M104a and the characteristics of the transistor M114 nor the relationship between the device characteristics of the NMOS diode M104b and the characteristics of the transistor M118 are disclosed. This leads to the problem that if the current ratio between the NMOS diode M104a and the transistor M114 is set to a specified ratio through an amperage adjustment made by changing the size of transistor, the circuit design suffers because the current ratio is not precisely proportional to the sizes of the transistors. Transistors that have different sizes have different current densities. This causes variations in the properties of the transistors and, as a consequence, may compromise data reading accuracy. However, the NMOS diode M104a and the transistor M114 are coupled in different ways and moreover, there is no restriction on their sizes. The same is true for the relationship between the NMOS diode M104b and the transistor M118. Generally, M104a and M104b are restricted to being the same size, with M114 and M118 being similarly restricted. Alternatively, the ratio of the sizes of M104a and M104b are restricted to being equal to the ratio of the sizes of M114 and M118. That is, the difference or ratio between the currents flowing in M104a and M104b and the difference or ratio between the currents flowing in M114 and M118 are important properties of this circuit and these two properties are independently controlled. In other words, the restriction on the amperage of M104a or M104b and the restriction on the amperage of M114 or M118 are independently given. In addition, a limit is placed on the gain of the differential amplifier circuit 134 by the output potential SENSEARY of M104a (or the output voltage SENSREF of M104b) serving as a current detecting device (Generally speaking, when the SENSEARY/SENSEREF potentials are in the vicinity of VCC, the gain decreases.) Therefore, there are constraints on the design that, if not satisfied, will cause the behavior of the circuit to become unstable.
Furthermore, if the NMOS diode M104a differs from the transistor M114 in structure, current variations occur between the devices and therefore correct data reading operation cannot be performed.
In some cases, the number of detecting units 130 installed differs from the number of detecting units 132 installed. For example, there is a case where one detecting unit 130 corresponds to one differential amplifier unit 134, while one detecting unit 132 corresponds to a plurality of differential amplifier units 134. In this case, the parasitic capacitance of the signal path of the detecting unit 130 becomes smaller than the parasitic capacitance of the signal path of the detecting unit 132, causing a difference in parasitic capacitance. This causes a difference in signal transmission speed and, consequently, creates the possibility of occurrences of data readout errors. In addition, if a correction capacitance is added to the signal path of the detecting unit 130 with the view to eliminate the difference in capacitance, the correction capacitance disadvantageously brings about an increase in the size of the circuit and in current consumption.
The conventional art shown in FIG. 1 does not disclose the wiring configuration of the high potential power source VCC and low potential power source VSS. That is, the conventional art gives little insight into problems which would arise depending on the power source wiring, such as a resistance characteristics to power source noise and the need to use wide power source wiring. In addition, the conventional art of FIG. 1 does not mention the arrangement of each transistor element. That is, the conventional art does not consider problems such as increased circuit area and an unsatisfactory noise shut-off effect which are caused depending on the arrangement of the elements.